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HIP1011D
Data Sheet November 1999 File Number 4725.1
Dual PCI Hot Plug Controller
The HIP1011D is the first IC available for independent control of two PCI Hot Plug slots. The HIP1011D has all the features and functionality of two single PCI Hot Plug slot controllers such as the HIP1011A but in the same foot print area. The HIP1011D is designed to be physically placed in close proximity to two adjacent PCI slots servicing each independently but reducing layout complexity and placement costs in assembly. It creates two independent power control solutions with discrete power MOSFETs and a few passive components. The four supplies +5V, +3.3V, +12V, and -12V for each slot are independently controlled. There are four integrated current sensing switches for the +12V and -12V and for the +5V and +3.3V supplies overcurrent protection is provided by sensing the voltage across external currentsense resistors. In addition, on-chip references are used to monitor the +5V, +3.3V and +12V outputs for undervoltage conditions. The two PWRON inputs control the state of the switches, one each for slot A and slot B outputs. During an overcurrent condition on any output, or an undervoltage condition on the +5V, +3.3V or +12V outputs, a LOW (0V) is asserted on the associated FLTN output and all associated switches are latched-off. The outputs servicing the adjacent slot are unaffected. The time to FLTN signal going LOW and MOSFET latch off is user determined by a single capacitor from each FLTN pin to ground. This added feature enables the HIP1011D to ignore system noise transients. The FLTN latch is cleared when the PWRON input is toggled low again. During initial power-up of the main VCC supply (+12V), the PWRON input is inhibited from turning on the switches, and the latch is held in the Reset state until the VCC input is greater than 10V. User programmability of the overcurrent threshold and turnon slew rate is provided. A resistor connected to the OCSET pin programs the overcurrent threshold for both slots. Capacitors connected to the gate pins set the turn-on rate.
Features
* Independent Power Control of 2 PCI Slots * Turn-Off Delay Time Adjustability * Internal MOSFET Switches for +12V and -12V Outputs * P Interface for On/Off Control and Fault Reporting * Adjustable Overcurrent Protection for All Eight Supplies * Provides Fault Isolation * Adjustable Turn-On Slew Rate * Minimum Parts Count Solution * No Charge Pump * 100ns Response Time to Over Current
Applications
* PCI Hot-Plug
Ordering Information
PART NUMBER HIP1011DCA HIP1011DCA-T TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 28 Ld SSOP Tape and Reel PKG. NO. M28.15
Pinout
HIP1011D (SSOP) TOP VIEW
M12VO_2 M12VG_2 PWRON_2 FLTN_2 VSS 12VG_2 12VO_2 12VO_1 12VG_1 1 2 3 4 5 6 7 8 9 28 M12VIN_2 27 3VISEN_2 26 3VS_2 25 5VISEN_2 24 5VS_2 23 3V5VG_2 22 12VIN_2 21 12VIN_1 20 3V5VG_1 19 5VS_1 18 5VISEN_1 17 3VS_1 16 3VISEN_1 15 M12VIN_1
OCSET 10 FLTN_1 11 PWRON_1 12 M12VG_1 13 M12VO_1 14
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
HIP1011D Typical Application
12V
-12V
SLOT 1
5V
3.3V
M12VIN_1 M12G_1 C1 M12VO_1 -12V BUS M12VIN_2 M12G_2 C2 M12VO_2 12VIN_1 12VG_1 12VO_1
5VISEN_1 R1 5VS_1 3V5VG_1 3V5VG_2 Q2 5VS_2 R2 5VISEN_2 3VISEN_1 R3 3VS_1 Q3 3.3V BUS 5V Q1
HIP1011D
C3 +12V BUS
C4 FROM SYSTEM CONTROLLER
12VIN_2 12VG_2 12VO_2 3VS_2 PWRON_1 PWRON_2 OCSET VSS FLTN_1 3VISEN_2 FLTN_2
Q4 R4 C5 C6
R5
OPT.
OPT.
TO SYSTEM CONTROLLER -12V 12V SLOT 2 3.3V
FIGURE 1.
2
5V BUS
HIP1011D Simplified Schematic (1/2 HIP1011D)
5VREF SET (LOW = FAULT) FAULT LATCH LOW = FAULT COMP
FLTN
+ 4.6V
INHIBIT RESET COMP + 2.9V
INHIBIT COMP + 10.6V
INHIBIT 12VIN 12VIN COMP + 12VIN 3V5VG 5VREF 5V ZENER REFERENCE 5VISEN + 5VS
12VIN
COMP LOW WHEN 12VIN < 10V + -
+
-
12VIN 12VIN POWER-ON RESET
3VS
3VISEN
12VIN COMP 100A VOCSET OCSET HIGH = FAULT + 12VIN 12VG + M12VIN + 12VIN 0.3
12VO 12VIN HIGH = SWITCHES ON PWRON COMP M12VIN + 0.7
GND
M12VG
M12VO
FIGURE 2.
3
HIP1011D Pin Descriptions
PIN NO. 15, 28 4, 11 20, 23 DESIGNATOR M12VIN FLTN 3V5VG FUNCTION -12V Input Fault Output 3.3V/5V Gate Output DESCRIPTION -12V Supply Input. Also provides power to the -12V overcurrent circuitry. 5V CMOS Fault Output; LOW = FAULT. An optional capacitor may be place from this pin to ground to provide additional immunity from power supply glitches. Drive the gates of the 3.3V and 5V MOSFETs. Connect a capacitor to ground to set the start-up ramp. During turn on, this capacitor is charged with a 25A current source. UV comparator disabled when this pin below 9.6V nominal. 12V supply input for IC and 12VO. Both 12VIns to be connected to a single +12V supply. Connect to the load side of the current sense resistor in series with source of external 3.3V MOSFET. Connect to source of 3.3V MOSFET. This connection along with (3VISEN) senses the voltage drop across the sense resistor. Connect to source of 5V MOSFET switch. This connection along with (5VISEN) senses the voltage drop across the sense resistor. Connect to the load side of the current sense resistor in series with source of external 5V MOSFET. Controls all four switches. High to turn switches ON, Low to turn them OFF.
21, 22 16, 27 17, 26 19, 24 18, 25 3, 12 6, 9
12VIN 3VISEN 3VS 5VS 5VISEN PWRON 12VG
12V Input 3.3V Current Sense 3.3V Source 5V Source 5V Current Sense Power On Control
Gate of Internal PMOS Connect a capacitor between 12VG and 12VO to set the start-up ramp for the +12V supply. This capacitor is charged with a 25A current source during start-up. UV comparator disabled when this pin >1.4Vnominal. Switched 12V Output Switched 12V output. Rated for 0.5A.
7, 8 2, 13 1, 14 10
12VO M12VG M12VO OCSET
Gate of Internal NMOS Connect a capacitor between M12VG and M12VO to set the start-up ramp for the M12V supply. This capacitor is charged with 25A during start-up. Switched -12V Output Overcurrent Set Switched 12V Output. Rated for 100mA. Connect a resistor from this pin to ground to set the overcurrent trip point of all eight switches. All eight over current trips can be programmed by changing the value of this resistor. The default (6.04k, 1%) is compatible with the maximum allowable currents as outlined in the PCI specification. Connect to common of power supplies.
5
VSS
Ground
4
HIP1011D
Absolute Maximum Ratings
12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V 12VO, 12VG, 3V5VG . . . . . . . . . . . . . . . . . . . .-0.5V to 12VIN +0.5V M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0V to +0.5V M12VO, M12VG . . . . . . . . . . . . . . . . . . . . . . VM12VIN-0.5V to +0.5V 3VISEN, 5VISEN . . . . . . . . . . -0.5V to the Lesser of 12VIN or +7.0V Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2KeV (HBM)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SSOP - Lead Tips Only)
Operating Conditions
12VIN Supply Voltage Range . . . . . . . . . . . . . . . . +10.8V to +13.2V 5V and 3.3V Input Supply Tolerances. . . . . . . . . . . . . . . . . . . . . . 10% 12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.5A M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.1A Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER 5V/3.3V SUPPLY CONTROL 5V Overcurrent Threshold 5V Overcurrent Threshold Voltage 5V Overcurrent Threshold Voltage 5V Undervoltage Trip Threshold
Nominal 5.0V and 3.3V Input Supply Voltages, 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IOC5V VOC5V_1 VOC5V_2 V5VUV t5VUV tON5V IOC3V VOC3V_1 VOC3V_2 V3VUV t3VUV V3V5VGenVth tON3V
See Figure 24, Typical Application VOCSET = 0.6V VOCSET = 1.2V
33 70 4.42 -
8 42 80 4.65 110 6.5 10 52 98 2.86 110 9.6 6.5 11.8 25.0 280 2
50 90 4.7 160 62 108 2.9 160 29 -
A mV mV V ns ms A mV mV V ns V ms V A s s
5V Undervoltage Fault Response Time 5V Turn-On Time (PWRON High to 5VOUT = 4.75V) 3V Overcurrent Threshold 3V Overcurrent Threshold Voltage 3V Overcurrent Threshold Voltage 3V Undervoltage Trip Threshold 3V Undervoltage Fault Response Time 3V5VG Undervoltage Enable Threshold Voltage 3V Turn-On Time (PWRON High to 3VOUT = 3.00V) 3V5VG Vout High Gate Output Charge Current Gate Turn-On Time (PWRON High to 3V5VG = 11V) Gate Turn-Off Time
C3V5VG = 0.022F, C5VOUT = 2000F, RL = 1 See Figure 24, Typical Application VOCSET = 0.6V VOCSET = 1.2V
41 89 2.74 -
C3V5VG = 0.022F, C3VOUT = 2000F, RL = 0.43
11.5 19 -
Vout_hi_35VG PWRON = High, FLTN = High IC3V5VG tON3V5V tOFF3V5V PWRON = High, V3V+5VG = 4V C3V5VG = 0.033F, 3V5VG Rising 10% to 90% C3V5VG = 0.033F, 3V5VG Falling 90% to 10%
5
HIP1011D
Electrical Specifications
PARAMETER +12V SUPPLY CONTROL On Resistance of Internal PMOS rDS(ON)12 PWRON = High, ID = 0.5A, TA = TJ = 25oC TA = TJ = 70oC Overcurrent Threshold Overcurrent Threshold 12V Undervoltage Trip Threshold Undervoltage Fault Response Time Gate Charge Current Turn-On Time (PWRON High to 12VG = 1V) Turn-Off Time -12V SUPPLY CONTROL On Resistance of Internal NMOS rDS(ON)M12 PWRON = High, ID = 0.1A, TA = TJ = 25oC TA = TJ = 70oC Overcurrent Threshold Overcurrent Threshold Gate Output Charge Current Turn-On Time (PWRON High to M12VO = -10.8V) Turn-Off Time M12VIN Input Bias Current CONTROL I/O PINS Supply Current OCSET Current Overcurrent Fault Response Time PWRON Threshold Voltage FLTN Output Low Voltage FLTN Output High Voltage FLTN Output Latch Threshold 12V Power On Enable Threshold 12V Power On Reset Threshold IVCC IOCSET tOC VTHPWRON VFLTN,OL VFLTN,OH VFLTN,TH VPOR,THrise VPOR,THfall IFLTN = 2mA IFLTN = 0 to -4mA FLTN High to Low transition VCC Voltage Rising VCC Voltage Falling 93 1.0 4.0 1.8 9.4 8.9 5.3 100 500 1.6 0.5 4.3 2.3 10 9.1 3 10.2 9.3 8 107 960 2.1 0.7 mA A ns V V V V V V IOC12V_1 IOC12V_2 ICM12VG tONM12V tOFFM12V IBM12VIN VOCSET = 0.6V VOCSET = 1.2V PWRON = High, V3VG = -10V CM12VG = 0.033F, CM12VO = 50F, RL = 120 CM12VG = 0.033F, M12VG Falling 90% to 10% PWRON = High 0.13 0.23 19 0.7 1.0 0.18 0.38 25 16 3 2.5 1 1.3 0.25 0.52 29 5 A A A ms s mA IOC12V_1 IOC12V_2 V12VUV t12VUV IC12VG tON12V tOFF12V PWRON = High, V12VG = 10V C12VG = 0.033F, 12VG Falling 90% - 10% C12VG = 0.022F, 12VG Rising 10% - 90% VOCSET = 0.6V VOCSET = 1.2V 0.6 1.25 10.25 19 0.3 0.35 0.75 1.50 10.6 110 25.0 16 3 0.35 0.50 0.9 1.8 10.8 29 A A V ns A ms s Nominal 5.0V and 3.3V Input Supply Voltages, 12VIN = 12V, M12VIN = -12V, TA = TJ = 0 to 70oC, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
6
HIP1011D Introduction
The HIP1011D is the first device designed to provide control and protection of the four PCI power supplies independently to two PCI slots. Like the widely used HIP1011 this device complies with the PCI Hot Plug specification facilitating the service, upgrading or expansion of PCI based servers without the need to power down the server. The HIP1011D protects against over current (OC) for the -12V, +12V, +3.3V, +5V and under voltage (UV) conditions for the +12V, +3.3V, +5V supplies. Figure 1 illustrates the typical implementation of the HIP1011D. Additional components for optimizing performance for particular applications, or desired features may be necessary. comparators. The +12V and -12V currents are sensed internally with pilot devices. Once any comparator trips, that output is fed through logic circuits resulting in the appropriate FLTN, (pin 4 or pin 11), going low, indicating a fault condition on that particular slot. Because of the internal current monitoring of the +12V and -12V switches, their programming flexibility is limited to ROCSET changes. The 3.3V and 5V over current trip points depend on both ROCSET and the value chosen for each sense resistor. Over current design guidelines and recommendations are as follows: 1. For PCI applications, set ROCSET to 6.04k, and use 5m 1% sense resistors (see Figure 24). 2. For non PCI specified applications, the following precautions and limitations apply: A. Do not exceed the maximum power of the integrated NMOS and PMOS. High power dissipation must be coupled with effective thermal management. The integrated PMOS has an rDS(ON) of 0.3. Thus, with 1A of steady load current on each of the PMOS devices the power dissipation is 0.6W. The thermal impedance of the package is 95 degrees Celsius per watt, limiting the average DC current on the 12V supply to about 1A on each slot and imposing an upper limit on the ROCSET resistor. Do not use an ROCSET resistor greater than 15k. The average current on the -12V supply should not exceed 0.7A. Since the thermal restrictions on the +12V supply are more severe, the +12V supply restricts the use of the HIP1011 to applications where the 12V supplies draw relatively little current. Since both supplies only have one degree of freedom, the value of ROCSET, the flexibility of programming is quite limited. For applications where more power is required on the +12V supply, contact your local Intersil sales representative for information on other Hot Plug solutions. B. Do not try to sense voltages across the external sense resistors that are less than 33mV. Spurious faults due to noise and comparator input sensitivity may result. The minimum recommended ROCSET value is 6k. This will set the nominal OC voltage thresholds at 52mV and 42mV for the 3.3V and 5V comparators respectively. This is the voltage level at which the OC fault (IOUT x RSENSE) will occur. C. Minimize VRSENSE so as to not significantly reduce the voltage delivered to the adapter card. Remember PCB trace and connector distribution voltage losses also need to be considered. Make sure that the RSENSE resistor can adequately handle the dissipated power. For best results use a 1% precision resistor with a low temperature coefficient. D. Minimize external FET rDS(ON). Low rDS(ON) or multiple MOSFETs in parallel are recommended. See Intersil for a complete selection of MOSFET offerings.
Key Feature Description and Operation
The HIP1011D, four power MOSFETs and a few passive components as configured in Figure 1, create a small yet complete power control solution for two PCI slots. It provides an OC trip level greater than the maximum PCI specified current for each supply to each slot. Over current monitoring and protection for the 3.3V and 5V supplies is provided by sensing the voltage across external current-sense resistors. For the +12V and -12V inputs, over current protection is provided internally. On-chip references are used to monitor the +5V, +3.3V and +12V outputs for under voltage conditions. During an over current condition on any output, or an under voltage condition on the +5V, +3.3V or +12V outputs, all slot specific MOSFETs are immediately latchedoff and a LOW (0V) is presented to the appropriate FLTN output. During initial power-up of the main VCC supply (+12V), the PWRON inputs are inhibited from turning on the switches, and the latch is held in the reset state until the VCC input is greater than 10V. After a fault has been asserted and FLTN is latched low cycling PWRON low then high will clear the FLTN latch. User programing of the OC thresholds for both controlled slots is provided by a single resistor connected to the OCSET pin along with Rsense. In addition delay time to latch off after a fault condition can be increased by increasing the FLTN to ground capacitance and the turnon ramp rate can be increased by increasing the gate pin capacitance.
Customizing Circuit Performance
Over Current (OC) Set Functionality and Resistor Choice
The HIP1011D allows easy custom programming of the over current (OC) levels of all 4 supplies simultaneously for both PCI slots by simply changing the resistor value between OCSET, (pin 10), and ground. The ROCSET value and the OCSET 100A current source sets a voltage that is used in each of eight comparators, (one for each supply for both slots). The voltages developed across the 3.3V and 5V sense resistors are applied to the inputs of their respective
7
HIP1011D
TABLE 1. SUPPLY +3.3V IOC +5.0V IOC +12V IOC -12V IOC HOW TO DETERMINE NOMINAL (10%) IOC FOR EACH SUPPLY ((100A x ROCSET)/11.5)/RRSENSE ((100A x ROCSET)/14.5)/RRSENSE (100A x ROCSET)/0.8 (100A x ROCSET)/3.3
Decoupling Precautions and Recommendations
For the HIP1011D proper decoupling is a particular concern during the normal switching operation and especially during a card crowbar failure. If a card experiences a crow bar short to ground, the supply to the other card will experience transients until the faulted card is isolated from the bus. In addition the common IC nodes between the two sides can fluctuate unpredictably resulting in a false latch-off of the second slot. Additionally to the mother board bulk capacitance, it is recommended that 10F capacitors be placed on both the +12V and -12V lines of the HIP1011D as close to the chip as possible.
Time Delay to Latch-Off
Time delay to latch-off allows for a predetermined delay from an OC or UV event to the simultaneous latch-off of all four supply switches of the affected slot by the HIP1011D. This delay period is set by the capacitance value to ground from the FLTN pins for each slot. This capacitance value tailors the FLTN signal going low ramp rate. This provides a delay to the fault signal latch-off threshold voltage, FLTN, Vth. By increasing this time, the HIP1011D delays immediate latchoff of the bus supply switches, thus ignoring transient OC and UV conditions. See additional information in the "Using the HIP1011DEVAL1 Platform" section of this data sheet. Caution: The primary purpose of a protection device such as the HIP1011D is to quickly isolate a faulted card from the voltage bus. Delaying the time to latch-off works against this primary concern so care must be taken when using this feature. Ensure adequate sizing of external FETs to carry additional current during time out period. Understand that voltage bus disruptions must be minimized for the time delay period in the event of a crow bar failure. Devices using an unadjustable preset delay to latch-off time present the user with the inability to eliminate these concerns increasing cost and the chance of additional ripple through failures.
Recommended PCB Layout Design Best Practices
To ensure accurate current sensing, PCB traces that connect each of the current sense resistors to the HIP1011D must not carry any load current. This can be accomplished by two dedicated PCB kelvin traces directly from the sense resistors to the HIP1011D, see examples of correct and incorrect layouts below in Figure 3. To reduce parasitic inductance and resistance effects, maximize the width of the high-current PCB traces.
CORRECT
INCORRECT
TO HIP1011D VS AND VISEN
TO HIP1011D VS AND VISEN
HIP1011D Soft Start and Turn-Off Considerations
The HIP1011D does allow the user to select the rate of ramp up on the voltage supplies. This start-up ramp minimizes inrush current at start-up while the on card bulk capacitors charge. The ramp is created by placing capacitors on M12VG to M12VO, 12VG to 12VO and 3V5VG to ground. These capacitors are each charged up by a nominal 25A current during turn on. The same value for all gate timing capacitors is recommended. A recommended minimum value of 0.033F as a smaller value may cause overcurrent faults at power up. This recommendation results in a nominal gate voltage ramp rate of 0.76V/ms. The gate capacitors must be discharged when a fault is detected to turn off the power FETs. Thus, larger caps slow the response time. If the gate capacitors are too large the HIP1011D may not be able to adequately protect the bus or the power FETs. The HIP1011D has internal discharge FETs to discharge the load when disabled. Upon turn-off these internal switches on each output discharge the load capacitance pulling the output to gnd. These switches are also on when PWRON is low thus an open slot is held at the gnd level. 8
CURRENT SENSE RESISTOR
FIGURE 3. SENSE RESISTOR PCB LAYOUT
HIP1011D Typical Performance Curves
340 1000 4.632 4.631 PMOS rON +12 (m) NMOS -12 rON NMOS rON -12 (m) 320 900 4.630 4.629 4.628 4.627 260 0 600 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC) 4.626 0 2.858 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC) 3.3 UV 2.859 2.860 2.862
5 UV 2.861 3.3V UVTRIP (V)
300 PMOS +12 rON 280
800
700
FIGURE 4. rON vs TEMPERATURE
10.59 100
5V UVTRIP (V)
FIGURE 5. UV TRIP vs TEMPERATURE
3V OCVth, VOCSET = 1.2V 85 12 UV TRIP (V) OC Vth (mV) 10.57 5V OCVth, VOCSET = 1.2V 70
10.55 55
3V OCVth, VOCSET = 0.6V 5V OCVth, VOCSET = 0.6V
10.53 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
40 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
FIGURE 6. 12 UV TRIP vs TEMPERATURE
FIGURE 7. OC Vth vs TEMPERATURE
6 +12V BIAS ABS +/-12V BIAS (MA) +12V THRESHOLDS (V) 5
10.0 +12V POWER ON ENABLE 9.75
4 -12V BIAS 3
9.5
9.25 +12V POWER ON RESET
2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
9.0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
FIGURE 8. BIAS CURRENT vs TEMPERATURE
FIGURE 9. 12V ENABLE AND RESET THRESHOLD VOLTAGES vs TEMPERATURE
9
HIP1011D Typical Performance Curves
1.5
(Continued)
0.4 VOCSET = 1.2V
+12V OVER CURRENT (A)
-12V OVER CURRENT (A)
1.25
VOCSET = 1.2V
0.3
1.0
0.2 VOCSET = 0.6V 0.1
0.75
VOCSET = 0.6V
0.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
FIGURE 10. +12V OVER CURRENT LEVEL vs TEMPERATURE
FIGURE 11. -12V OVER CURRENT vs TEMPERATURE
102 FLTN LATCH OFF THRESHOLD (V)
2.4
101 IOC SET (A)
2.35
100
2.3
99
2.25
98 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
2.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
FIGURE 12. OCSET CURRENT vs TEMPERATURE
FIGURE 13. FLTN LATCH-OFF THRESHOLD VOLTAGE vs TEMPERATURE
100 OV / UV TO FAULT RESPONSE TIME (ns)
90
80
70
60 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (oC)
FIGURE 14. OVER CURRENT AND UNDERVOLTAGE TO FLTN RESPONSE TIME vs TEMPERATURE
10
HIP1011D Using the HIP1011DEVAL1 Platform
General and Biasing Information
The HIP1011DEVAL1 platform (Figure 24) comes as a three part set consisting of 1 mother board emulator and 2 load cards. This evaluation platform allows a designer to evaluate and modify the performance and functionality of the HIP1011D in a simple environment. Test point numbers (TP#) correspond to the HIP1011D device (U5) pin numbers thus TP3 and TP12 are PWRON_2 and PWRON_1 respectively. These 2 pins are the HIP1011D control inputs for each of the 2 integrated but independent PCI power controllers in the HIP1011D. On the HIP1011DEVAL1 platform are 4 HUF76132SK8, (11.5m, 30V, 11.5A) N-Channel power MOSFETs, (Q1Q4) these are used as the external switches for the +5V and +3.3V supplies to the load card connectors, P1 and P2. Current sensing is facilitated by the four 5m 1W metal strip resistors (R1-R4), the voltages developed across the sense resistors are compared to references on board the HIP1011D. The HIP1011DEVAL1 platform is powered through the J1 to J5 connector jacks near the top of the board, see Table 2 for bias voltage assignments.
TABLE 2. HIP1011DEVAL1 BIAS ASSIGNMENTS J1 GND J2 +5V J3 -12V J4 +12V J5 +3.3V
Evaluating Time Delay to Latch-Off
Provided for delay to latch-off evaluation are 2 locations for 1206 SMD capacitors, C7 and C8. Filling these locations places a capacitor to ground from each of the HIP1011D FLTN pins thus tailoring the FLTN signal going low ramp rate. This provides a delay to the fault signal latch-off threshold voltage, FLTN Vth. By increasing this time the HIP1011D delays immediate latch-off of the bus supply switches, thus ignoring transient OC and UV conditions. See Table 3 illustrating the time it takes for switch gate turn-off from the FLTN start of response to an OC or UV condition. The FLTN response to an OC or UV condition is 110ns. See Figures 20 through 23 for waveforms. The intent of any protection device is to isolate the supply quickly so a faulty card does not drag down a supply. A longer latch-off delay results in less isolation from a faulty card to supply.
TABLE 3. C7 AND C8 VALUE FLTN to Gate Response OPEN 0.1s 0.001F 0.44s 0.01F 2.9s 0.1F 28s
FLTN 3V5VG FLTN, Vth
After properly biasing the HIP1011D and ensuring there is an adequate ground return from the HIP1011DEVAL1 platform to the power supplies, (otherwise anomalous and unpredictable results will occur) signal the PWRON inputs low then insert the load cards as shown in Figure 15. Signaling either or both PWRON pins high (>2.4V) will turn on the appropriate FET switches and apply voltage to the load cards.
FIGURE 16. TIMING DIAGRAM
10ms 1ms 100s 10s
LOAD CARDS 1s 100ns 10ns 1ns OPEN
0.001F
0.01F
0.1F
1F
10F
FIGURE 17. TYPICAL OC/UV TO VG RESPONSE vs FLTN CAP
HIP1011D
FIGURE 15. cORRECT INSTALLATION OF LOAD CARDS
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HIP1011D Typical Performance Curves (Continued)
SUPPLY CURRENT
SUPPLY CURRENT
CH3
CH2
ENABLE 2
CH2
ENABLE 2
CH1
ENABLE 1
CH1 ENABLE 1
CH1 AND CH2 VOLTAGE (5V/DIV) CH3 CURRENT (2A/DIV)
TIME (100ms/DIV)
CH1 AND CH2 VOLTAGE (5V / DIV) CH3 CURRENT (2A/DIV)
TIME (100ms/DIV)
FIGURE 18. HIP1011DEVAL1 3.3V SUPPLY CURRENT AS EACH SLOT CONTROLLER TURNS ON INTO LOAD CARD
FIGURE 19. HIP1011DEVAL1 3.3V SUPPLY CURRENT AS CONTROLLER 1 TURNS ON INTO SHORTED LOAD CARD
VG
VG
FLTN
FLTN
VOLTAGE (2V/DIV)
TIME (1s /DIV) FLTN = OPEN
VOLTAGE (2V/DIV)
TIME (1s /DIV) FLTN = 0.001F
FIGURE 20. FLTN TO 35VG DELAY
FIGURE 21. FLTN TO 35VG DELAY
VG
VG
FLTN
FLTN
VOLTAGE (2V/DIV)
TIME (2s/DIV) FLTN = 0.01F
VOLTAGE (2V/DIV)
TIME (10s/DIV) FLTN = 0.1F
FIGURE 22. FLTN TO 35VG DELAY
FIGURE 23. FLTN TO 35VG DELAY
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HIP1011D
12V -12V
J3 -12V BUS C1 M12VO_1 J1 C2 M12VO_2 J4 +12V BUS C3 12VIN_1 12VG_1 12VO_1 12VIN_2 12VG_2 12VO_2 TP3 TP12 3VS_2 PWRON_1 PWRON_2 OCSET VSS FLTN_1 3VISEN_2 FLTN_2 TP11 R5 R6 R7 C7
No Pop
P1
5V
3.3V
M12VIN_1 M12G_1
5VISEN_1 R1 5VS_1 3V5VG_1 Q1 5V BUS J2
M12VIN_2 M12G_2
3V5VG_2 Q2 5VS_2 R2 5VISEN_2
HIP1011D
U1
3VISEN_1 R3 3VS_1 Q3 3.3V BUS Q4 R4
C5
C6
J5
C4
C8
No Pop
TP4
D1
D2
-12v
12v
P2
3.3v
5v
FIGURE 24.
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HIP1011D
TABLE 4. HIP1011DEVAL1 BOARD COMPONENT LISTING COMPONENT DESIGNATOR U1 Q1, Q2, Q3, Q4 R1 - R4 C1 - C6 R5 C7, C8 (Not Provided) R6, R7 D1, D2 TP1 - TP28 P1, P2 RL1 RL2 RL3 RL4 CL1, CL2 CL3, CL4 COMPONENT NAME HIP1011DCB PCI HotPlug Controller HUF76132SK8 Sense Resistor for 3.3V and 5V Supplies Gate Timing Capacitors Over Current Set Resistor Latch-Off Delay Capacitors LED Series Resistors Fault Indicating LED Test Point for Corresponding Device Pin Number Connectors for Load Cards 3.3V Load Board Resistor 5.0V Load Board Resistor +12V Load Board Resistor -12V Load Board Resistor +3.3V and +5.0V Load Board Capacitors +12V and -12V Load Board Capacitors
RL1 3.3V CL1 RL2 5.0V CL2 RL3 +12V CL3 RL4 -12V CL4
COMPONENT DESCRIPTION Intersil, HIP1011DCB Dual PCI HotPlug Controller Intersil, HUF76132SK8, 11.5m, 30V, 11.5A Logic Level N-Channel MOSFET Dale, WSL-2512 5m Metal Strip Resistor 0.033F 805 Chip Capacitor 6k 805 Chip Resistor Place provided for 805 Chip Cap 470 805 Chip Resistors Green SMD LED
Sullins EZM06DRXH 1.1, 10W 2.5, 10W 47, 5W 240, 2W 2200F 100F
FIGURE 25. LOAD BOARD (2x)
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HIP1011D Shrink Small Outline Plastic Packages (SSOP)
N INDEX AREA E -B1 2 3 L SEATING PLANE -AD -CA 0.25 0.010 h x 45o GAUGE PLANE H 0.25(0.010) M BM
M28.15
28 LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D MIN 0.053 0.004 0.008 0.007 0.386 0.150 MAX 0.069 0.010 0.061 0.012 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.20 0.18 9.81 3.81 MAX 1.75 0.25 1.54 0.30 0.25 10.00 3.98 NOTES 9 3 4 5 6 7 8o Rev. 0 2/95
A1 0.10(0.004) A2 C
E e H h L N
e
B 0.17(0.007) M C AM BS
0.025 BSC 0.228 0.0099 0.016 28 0o 8o 0.244 0.0196 0.050
0.635 BSC 5.80 0.26 0.41 28 0o 6.19 0.49 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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